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IP Corner
Everything but the kitchen sink:
The increasing complexity of feature definition in today’s designs
By Doug Ridge, IP Strategic Sourcing Manager, eSilicon
While thinking about how much functionality we want to get into a single chip these days, the phrase “everything but the kitchen sink” came to mind. That started me on a trail that ended with finding that this phrase originates from the turn of the twentieth century. It was used to describe what happened when people who moved house wanted to take all of their belongings with them. The porcelain kitchen sink was heavy, connected to a variety of plumbing and often bolted down, making it difficult to move. So when people did move, they took “everything but the kitchen sink” with them.
Shrinking process geometries are continuing to allow us to squeeze more functionality into a device while reducing power consumption and cost and increasing performance. As a result, product planning and marketing teams are now raising the bar and setting higher goals for their ASICs than they would previously have considered.
Through our rose colored glasses this all looks great for future products, but when we take those glasses off to look at just how we achieve those goals, things look a lot different. Defining what we are going to create and understanding the unit price and NRE implications now becomes a significant sink for time and effort.
What did we have custom made?
Just considering the memory requirements is eye-opening when we see that in current generation designs the memory content can exceed 50 percent of the chip’s area and power. To address this, eSilicon provides custom memory solutions that are ultra-high speed (UHS), ultra-high density (UHD), ultra-low voltage (ULV) and ultra-low power (ULP). As Manish Bhatia, custom IP senior product marketing manager at eSilicon, pointed out “We are seeing an increased focus on memory solutions that go beyond mainstream and the value that eSilicon brings can, for example, reduce the power consumption by 10-20 percent. In other cases we have increased the performance of an embedded processor by 20 percent through a custom cache implementation.”
How do we take it all with us?
Beyond the high-level feature set of interfaces, memories, processors, etc., we also need to understand the impact of different IP choices from the basic building blocks of standard cells, to processors and processor subsystems. Do I need a seven-track standard cell library to minimize size and also a nine- or ten-track library to hit critical-path timing? Do I need high-density or high-performance memories and from whom? What performance and feature set do I need for my processor and should I use multiple processors or a single one? Has the IP been proven in silicon at my chosen process node and has anyone developed an ASIC with this particular pairing of interface and controller?
Entering the game to address these questions are the eSilicon pre-sales teams. On an increasingly regular basis, they are being brought in as trusted advisors by customers to help understand the trade-offs of different features in a design and ultimately to help architect the system and hit unit price and NRE goals. With a number of customer designs that include more than a dozen IP cores from several different IP partners, it is understandable that customers want to leverage their expertise.
In a recent conversation with Bill Isaacson, who heads eSilicon’s customer engineering team, we discussed a number of iterations of a customer’s IP content in their current design. “The IP list is morphing almost every time we meet. They have great ideas and goals for this device and we are able to leverage eSilicon expertise and pull in individual experts to help turn those ideas into reality.”
Getting the eSilicon teams involved early might mean a longer pre-sales engagement, but developing these truly synergistic relationships with customers has all-around benefits. It enables our customers to turn the handle on products that are right first time and hit the market with the right balance of features and cost to be highly successful.
In addition to the talent of the eSilicon customer engineering teams and the proven processes they follow, the engineers leverage eSilicon’s internally generated tools for die size estimation. These tools are constantly being enhanced allowing the teams to quickly and realistically understand NRE and unit costs. The “what if” product planning scenarios are assessed confidently and customers can then narrow in on the right options at a much faster rate than they typically would be able to by themselves.
So when it looks like you are being tasked with trying to put “everything but the kitchen sink” into a design, it’s worth talking to Bill’s team and other experts inside eSilicon to understand precisely how your goals can be achieved.
If you have any questions or comments for the author, please email ipcorner@esilicon.com
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