eSilicon

   Issue #14, April 2011

A Newsletter from eSilicon   

CEO Corner

IP Corner

eSilicon Blogs

eSilicon News

Industry News

Upcoming Events

  • Rob Cadman, 
eSilicon's VP & GM of the EMEA Region, will deliver the opening remarks at the VIP dinner at GSA’s Israel Executive Forum Tel Aviv, Israel, May 3, 2011
  • CEO Jack Harding will participate in the panel discussion Innovation in Smart Phone Technology Needs and Drivers for Future Growth at GSA & IET International Semiconductor Forum  — Munich, Germany, May 11, 2011
  • Join us at TSMC’s 2011 China Technology Symposium — Shanghai, China May 31, 2011
  • CEO Jack Harding will join Hogan’s Heroes, a DAC favorite, for a panel discussion on The Reaggregation of Ecosystem Value — DAC, San Diego, CA, June 7, 2011, booth 3421, 11:00 AM-12:00 PM
  • Patrick Soheili, GM and VP, IP business unit, will deliver a series of IP Talks held by ChipEstimate.com, also at DAC 2011. Stop by to hear about using custom memories to optimize your chip for performance, power and cost — DAC, San Diego, CA, June 6-8, 2011, ChipEstimate.com booth 1731

CEO Corner
 

Don't get left behind
By Jack Harding

Semiconductor Manufacturing Services, or SMS, is a megatrend that will sweep through the semiconductor industry at an increasing rate until its adoption becomes inevitable by all but the world’s very largest semiconductor companies. SMS is the outsourcing of internal operations activities that include supply chain management, commodity acquisition, yield management, supplier audit, second source qualification, test time optimization, urgent subject matter expert deployment and logistics. In short, SMS is the so-called “back end” currently executed by a thousand teams ranging in size from 5-50 employees; and doing it for fewer, more complex chips, with greater expense and more challenged results.

eSilicon pioneered the SMS business model. Over the past several years many companies have enjoyed the benefits of SMS, and they are substantial. Consider these:

  • Guaranteed future pricing whereby eSilicon takes all the commodity pricing risk.
  • OPEX reduction and a switch to a variable cost model. The operations cost is in the unit price. Those resources can be deployed to mission critical assignments.
  • Financing of the WIP and, therefore, improved cash flow.
  • Access to aggregated expertise to resolve the most challenging issue.
  • Unparalleled visibility to production and product information through our patented eSilicon Access® production management system. Developed over a decade, eSilicon Access is the most complete and sophisticated semiconductor IT system in the world.
  • And….your unit cost will stay the same or even go down…day one.

 As any ops team stares into the abyss of 40nm development and beyond, can they deliver the guaranteed results of the SMS model? And if they’re wrong? All one can do is to listen to the regret and excuses…but they’ll still be wrong.

The fact is the internal ops model makes no more sense today than developing your own EDA tools or having your own fab. The focus is wrong, the complexity is too great, and the economics are now, “bet the company.” Semiconductor companies need a partner that will take the risks they should not and guarantee the price for the next five years…no internal ops team can do that.

SMS is at the same tipping point we have seen in every other part of the semiconductor food chain that became new industry. The same dynamics and economics are at work.

Watch as the next major outsourcing shift in semiconductors defines the winners and losers for the next decade.

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IP Corner

Everything but the kitchen sink:
The increasing complexity of feature definition in today’s designs
By Doug Ridge, IP Strategic Sourcing Manager, eSilicon

While thinking about how much functionality we want to get into a single chip these days, the phrase “everything but the kitchen sink” came to mind. That started me on a trail that ended with finding that this phrase originates from the turn of the twentieth century. It was used to describe what happened when people who moved house wanted to take all of their belongings with them. The porcelain kitchen sink was heavy, connected to a variety of plumbing and often bolted down, making it difficult to move. So when people did move, they took “everything but the kitchen sink” with them.

Shrinking process geometries are continuing to allow us to squeeze more functionality into a device while reducing power consumption and cost and increasing performance. As a result, product planning and marketing teams are now raising the bar and setting higher goals for their ASICs than they would previously have considered.

Through our rose colored glasses this all looks great for future products, but when we take those glasses off to look at just how we achieve those goals, things look a lot different. Defining what we are going to create and understanding the unit price and NRE implications now becomes a significant sink for time and effort.

What did we have custom made?
Just considering the memory requirements is eye-opening when we see that in current generation designs the memory content can exceed 50 percent of the chip’s area and power. To address this, eSilicon provides custom memory solutions that are ultra-high speed (UHS), ultra-high density (UHD), ultra-low voltage (ULV) and ultra-low power (ULP). As Manish Bhatia, custom IP senior product marketing manager at eSilicon, pointed out “We are seeing an increased focus on memory solutions that go beyond mainstream and the value that eSilicon brings can, for example, reduce the power consumption by 10-20 percent. In other cases we have increased the performance of an embedded processor by 20 percent through a custom cache implementation.”

How do we take it all with us?
Beyond the high-level feature set of interfaces, memories, processors, etc., we also need to understand the impact of different IP choices from the basic building blocks of standard cells, to processors and processor subsystems. Do I need a seven-track standard cell library to minimize size and also a nine- or ten-track library to hit critical-path timing? Do I need high-density or high-performance memories and from whom? What performance and feature set do I need for my processor and should I use multiple processors or a single one? Has the IP been proven in silicon at my chosen process node and has anyone developed an ASIC with this particular pairing of interface and controller?

Entering the game to address these questions are the eSilicon pre-sales teams. On an increasingly regular basis, they are being brought in as trusted advisors by customers to help understand the trade-offs of different features in a design and ultimately to help architect the system and hit unit price and NRE goals. With a number of customer designs that include more than a dozen IP cores from several different IP partners, it is understandable that customers want to leverage their expertise.

In a recent conversation with Bill Isaacson, who heads eSilicon’s customer engineering team, we discussed a number of iterations of a customer’s IP content in their current design. “The IP list is morphing almost every time we meet. They have great ideas and goals for this device and we are able to leverage eSilicon expertise and pull in individual experts to help turn those ideas into reality.”

Getting the eSilicon teams involved early might mean a longer pre-sales engagement, but developing these truly synergistic relationships with customers has all-around benefits. It enables our customers to turn the handle on products that are right first time and hit the market with the right balance of features and cost to be highly successful.

In addition to the talent of the eSilicon customer engineering teams and the proven processes they follow, the engineers leverage eSilicon’s internally generated tools for die size estimation. These tools are constantly being enhanced allowing the teams to quickly and realistically understand NRE and unit costs. The “what if” product planning scenarios are assessed confidently and customers can then narrow in on the right options at a much faster rate than they typically would be able to by themselves.

So when it looks like you are being tasked with trying to put “everything but the kitchen sink” into a design, it’s worth talking to Bill’s team and other experts inside eSilicon to understand precisely how your goals can be achieved.

If you have any questions or comments for the author, please email ipcorner@esilicon.com

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